As shown in FIGS. 1a through 1e, the conventional methods of making a stack of capacitors, in particular for creating Dynamic Random Access Memory consist in forming, on a silicon substrate 1, comprising a highly doped area 2 adjacent to a main surface of the substrate, then, on the main surface of the substrate, a stack of successive layers alternately of dielectric material 4, 6, 8, of SiO2 for instance, and of polycrystalline silicon (poli Si) 5, 7, sandwiched between layers of dielectric material 4, 6 8 (FIG. 1a). A hole 9 is etched through the stack of successive layers alternately of dielectric material 4, 6, 8 and of poly Si 5, 7, to expose the surface of the highly doped area 2 of the silicon substrate.
As shown in FIG. 1b, a layer of polycrystalline silicon is then deposited on the surface of the external layer 8 of SiO2 of the stack, as well as on the walls of the hole 9, in order to shunt the layers of polycrystalline silicon 5 and 7 sandwiched between the SiO2 layers 4, 6 and 8.
As shown in FIG. 1c, SiO2 layers 4, 6 and 8 are eliminated to form an arborescent structure; its trunk is made up of the part of the poly Si layer 10 coating the walls of the hole 9, and its branches are made up of the layers of polycrystalline silicon 5 through 7 of the stack and the part of the polycrystalline silicon layer 10 initially coating the SiO2 external layer 8.
As shown in FIG. 1d, a thin layer of dielectric material, SiO2 for instance, is formed on this arborescent structure of polycrystalline silicon, either by deposit, or by thermal oxidation of polycrystalline silicon, in such a way that it leaves a void in the central hole 9 and spaces in between the polycrystalline silicon branches 5, 6 [should be 7] and 10 and the substrate 1.
The voids of the arborescent structure are then filled in, and the arborescent structure is coated with polycrystalline silicon, as shown in FIG. 1e. 
Contacts are then created on the polycrystalline silicon coating.
This method has several drawbacks.
First of all, applying a deposit of dielectric material and of polycrystalline silicon calls for the use of two distinct chambers.
On the other hand, the lack of selectivity between the SiO2 layers that are sandwiched between the polycrystalline silicon layers and all the other surrounding SiO2 layers, such as passivation layers, insulating filling material, etc., harms the method and requires the use of barrier levels.
Finally, since the conductive polysilicon layers are being sandwiched in between dielectric layers, the method calls for additional masking steps to etch a hole through the stack, in a way to shunt the conductive layers with a polycrystalline silicon deposit inside the holes.